1. Field of the Invention
The present invention relates generally to bus drivers used in digital electronics, and more specifically to CMOS open drain bus drivers.
2. Discussion of the Related Art
A bus driver is a circuit that amplifies a bus data or control signal sufficiently to ensure valid reception of that signal at the destination. Bus drivers, which are typically controlled with normal logic levels, increase the driving capability of other devices, such as microprocessors, which themselves may be capable of driving no more than a single load.
FIG. 1 illustrates a conventional complementary metal-oxide semiconductor (CMOS) bus driver 20. The driver 20 includes a NAND gate 30 and an open drain I/O driver 40. The NAND gate 30 includes p-channel transistors M1, M2, and n-channel transistors M3, M4, all connected substantially as shown. The DATA input is coupled to the gates of transistors M2, M3, and the ENABLE input is coupled to the gates of transistors M1, M4. The drains of transistors M1, M2 are coupled to the high reference voltage VDD_INT, and the source of transistor M4 is coupled to the low reference voltage VSS_INT (which is typically ground).
An open drain driver is a type of structure found in certain CMOS logic families. The output of an open drain driver is characterized by an active transistor pull-down for taking the output to a low voltage level and no pull-up device. The pull-down transistor is normally an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Resistive pull-ups are generally added to provide the high-level output voltage. In the open drain driver 40, n-channel transistor M5 is the pull-down device and resistor R1 serves as the resistive pull-up. The drain of transistor M5 serves as the output VOUT. Resistor R1 is coupled to the high reference voltage VDD_EXT, and the source of transistor M5 is coupled to the low reference voltage VSS_EXT (typically ground).
The bus driver 20 is an example of a bus driver having a final open drain stage. This type of driver is used in the well-known Inter Integrated Circuit bus (also known as the Inter-IC or I2C bus). In many bus drivers of this type it is common for all of the driver stages to use a common internal ground, except for the final open drain stage which uses its own external ground. In other words, the open drain transistor of the final open drain stage typically has its own external source of bias and ground. Thus, in the bus driver 20 the internal low reference voltage VSS_INT is isolated from the external low reference voltage VSS_EXT.
When the external reference voltage VSS_EXT is connected to simultaneously switching outputs (SSO) circuitry, undershoot noise can occur on the VSS_EXT line. SSO is a well-known potential source of system noise, and SSO noise is often the largest component in the noise budget. Specifically, SSO causes rapid current changes in the power and ground buses. Because of supply pin inductance, this current change causes bus voltage fluctuation, and thus reduces core and input noise margins. This noise can cause the driver circuit to generate false logic states, which is highly undesirable.
One common technique for attempting to remedy the SSO noise problem involves substantial modification to the integrated circuit package to reduce the power path inductance. Also, the number of ground pins can be increased to reduce the ground noise. In general, these modifications are undesirable due to constraints they can place on circuit density, layout and cost of implementation.
Thus, there is a need for an apparatus and/or method which overcomes these and other disadvantages. Namely, there is a need for a way to reduce the undesirable effects of undershoot ground line noise in bus drivers having a final open drain stage.
The present invention advantageously addresses the needs above as well as other needs by providing a driver that includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has a gate and a conducting path with the gate coupled to the input node and the conducting path coupled in series with the output node and the first reference node. The noise immunity circuitry is configured to keep the output node uncoupled from the first reference node during an occurrence of noise in a first reference voltage applied to the first reference node that causes the first transistor to change from an off state to an on state.
Another version of the present invention provides a driver that includes an input node, an output node, a first reference node, means for uncoupling the output node from the first reference node in response to an input voltage applied to the input node, and means for keeping the output node uncoupled from the first reference node during an occurrence of noise in a first reference voltage applied to the first reference node.
Another version of the present invention provides a method of performing a driver function. The method includes the steps of: receiving an input voltage at an input node; receiving a first reference voltage at a first reference node; uncoupling an output node from the first reference node in response to the input voltage; and keeping the output node uncoupled from the first reference node during an occurrence of noise in the first reference voltage.
Yet another version of the present invention provides a method of performing a driver function. The method includes the steps of: receiving an input voltage at an input node; receiving a first reference voltage at a first reference node; establishing a first transistor having a gate and a conducting path with the gate coupled to the input node and the conducting path coupled in series with an output node and the first reference node; turning the first transistor off in response to the input voltage; and keeping the output node uncoupled from the first reference node during an occurrence of noise in the first reference voltage that causes the first transistor to change from an off state to an on state.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.